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CDP1826C
March 1997
CMOS 64-Word x 8-Bit Static RAM
Description
The CDP1826C is a general purpose, fully static, 64-word x 8-bit random-access memory, for use in CDP1800-series or other microprocessor systems where minimum component count and/or price performance and simplicity in use are desirable. The CDP1826C has 8 common data input and data-output terminals with three-state capability for direct connection to a standard bidirectional data bus. Two chip-select inputs - CS1 and CS2 - are provided to simplify memory-system expansion. An additional select pin, CS/A5, is provided to enable the CDP1826C to be selected directly from the CDP1800 multiplexed address bus without additional latching or decoding. In an 1800 system, the CS/A5 pin can be tied to any MA address line from the CDP1800 processor. A TPA input is provided to latch the high-order bit of this address line as a chip-select for the CDP1826C. If this CS/A5 input is latched high, and if CS = 1 and CS2 = 0 at the appropriate time in the memory cycle, the CDP1826C will be enabled for writing or reading. In a non-1800 system, the TPA pin can be tied high, and the CS/A5 pin can be used as a normal address input. The six input-address buffers are gated with the chip-select function to reduce standby current when the device is deselected, as well as to provide for a simplified power down mode by reducing address buffer sensitivity to long fall times from address drivers which are being powered down. Two memory control signals, MRD and MWR, are provided for reading from the writing to the CDP1826C. The logic is designed so that MWR overrides MRD, allowing the chip to be controlled from a single R/W. A CHIP ENABLE OUTPUT is provided for daisy-chaining to additional memories or I/O devices. This output is high whenever the chip-select function selects the CDP1826C, which deselects any other chip which has its CS input connected to the CDP1826C CEO output. The connected chip is selected when the CDP1826C is deselected and the MRD input is low. Thus, the CEO is only active for a read cycle and can be setup so that a CEO of another device can feed the MRD of the CDP1826C, which in turn selects a third chip in the daisy chain. The CDP1826C has a recommended operating voltage of 4.5V to 5.5V and is supplied in 22 lead dual-in-line plastic packages (E suffix). The CDP1826C is also available in chip form (H suffix).
Features
* Ideal for Small, Low-Power RAM Memory Requirements in Microprocessor and Microcomputer Applications * Interfaces with CDP1800-Series Microprocessors Without Additional Address Decoding * Daisy Chain Feature to Further Reduce External Decoding Needs * Multiple Chip-Select Inputs for Versatility * Single Voltage Supply * No Clock or Precharge Required.
Ordering Information
PACKAGE PDIP TEMP. RANGE -40oC to +85oC PART NUMBER CDP1826CE PKG. NO. E22.4
Pinout
CDP1826C (PDIP) TOP VIEW
BUS 0 1 BUS 1 2 BUS 2 3 BUS 3 4 BUS 4 5 BUS 5 6 BUS 6 7 BUS 7 8 CS1 9 CS2 10 VSS 11 22 VDD 21 A0 20 CS/A5 19 A1 18 A2 17 A3 16 A4 15 TPA 14 MRD 13 MWR 12 CEO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1311.2
6-47
CDP1826C
CLEAR WAIT
ADDR BUS TPA
N0 - N2 MRD ADDR BUS TPB TPA Q DATA CPU CDP1800 SERIES MRD MWR
ROM
RAM CDP1826C MRD
SCO SCI INTERRUPT DMA - IN DMA OUT
I/O
CONTROL
CEO
EF1 - EF4
8-BIT BIDIRECTIONAL DATA BUS
FIGURE 1. TYPICAL CDP1802 MICROPROCESSOR SYSTEM
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CDP1826C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1826C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA Power Dissipation Per Package (PD) TA = -40oC to +60oC (Package Type E) . . . . . . . . . . . . . . 500mW TA = +60oC to +85oC (Package Type E). . . . . . Derate Linearly at 12mW/oC to 200mW TA = -55oC to +100oC (Package Type D) . . . . . . . . . . . . . 500mW TA = +100oC to +125oC (Package Type D). . . . Derate Linearly at 12mW/oC to 200mW
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CDP1826C
PARAMETER DC Operating Voltage Range Input Voltage Range Input Signal Rise or Fall Time, VDD = 5V
SYMBOL
MIN 4 VSS
MAX 6.5 VDD 10
UNITS V V s
tR, tF
-
Static Electrical Specifications
At TA = -40oC to +85oC, VDD = 5V 5%, Except as Noted: CONDITIONS LIMITS CDP1826C
PARAMETER Quiescent Device Current Output Low (Sink) Current BUS CEO Output High (Source) Current BUS CEO Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Leakage Current Operating Device Current (Note 2) Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES:
SYMBOL IDD IOL
VO (V) 0.4 0.4
VIN (V) 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD 0, VDD
MIN 1.6 0.8 -1.0 -0.6 VDD -0.1 3.5 -
(NOTE 1) TYP 5 3.2 1.6 -1.5 -1.0 0 VDD 0.1 5 0.1 5 10
MAX 50 0.1 1.5 1 10 1 7.5 15
UNITS A mA mA mA mA V V V V A mA A pF pF
IOH
VDD -0.4 VDD -0.4
VOL VOH VIL VIH IIN IOPER IOUT CIN COUT
Any Input 0, VDD -
1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1s.
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CDP1826C Signal Descriptions
A0 - A4, CS/A5 (Address Inputs): These inputs must be stable prior to a write operation, but may change asynchronously during Read operations. In an 1800 system, the multiplexed high-order address bit at pin CS/A5 can be latched at the end of TPA. A high level will provide a valid chip select for the CDP1826C. The low-order address bit which appears after TPA is used for data word selection. In non-1800 systems, TPA can be tied high to disable the latch and allow the CS/A5 pin to function as a normal address input. BUS 0 - BUS 7: 8-bit three-state common input/output data bus. TPA: High-order address strobe input. The high-order address bit at input CS/A5 is latched on the high-to-low transition of the TPA input. Tie TPA high to disable the CS/A5 latch feature. CS1, CS2 (Chip Selector): Either chip select (CS1 or CS2), when not valid, powers down the chip, disables READ and WRITE functions, and gates off the address and output buffers. MRD, MWR: Read and Write control signals. MWR overrides MRD, allowing the CDP1826C to be controlled from a single R/W line. CEO (Chip Enable Output): Allows daisy chaining to additional memories. CEO is high whenever the CDP1826C is selected. CEO is only active (low) for a Read cycle with the CDP1826C deselected and the MRD input low. VDD, VSS: Power supply connections.
BUS 0 A0 A1 A2 A3 A4 CS/A5 INPUT ADDRESS BUFFERS XY DECODE 64 x 8 MATRIX INPUT/OUTPUT DATA BUFFERS AND CONTROL BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7
D TPA C
Q
CS1 CS2 MWR MRD CEO
FIGURE 2. FUNCTIONAL DIAGRAM
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CDP1826C
1800 CLOCK
A5 TPA
MRD
CEO
BUS
VALID DATA
VALID DATA
RAM CYCLE CS1 = 1, CS2 = 0
(RAM SELECTED)
ROM CYCLE
(RAM DESELECTED)
OPERATING MODES CS1 * CS2 I I I O O X X I I I O O I I I I I X X (NOTE 1) CS/A5 I I I X X O O X X X X X
FUNCTION CDP1800 Mode Write Read Deselect Deselect Deselect Deselect Deselect Non-CDP1800 Mode Write Read Deselect Deselect Deselect NOTE:
MRD X O I I O I O X O I I O
MWR O I I X X X X O I I X X
TPA
CEO I I I I O I O I I I I O
1. For CDP1800 Mode, refers to high order memory address bit level at time when TPA place.
transition takes
FIGURE 3. CHIP ENABLE OUTPUT TIMING WAVEFORMS FOR CDP1800 BASED SYSTEMS
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CDP1826C
Dynamic Electrical Specifications At TA = -40 to +85oC, VDD = 5V 5%, Input tR, tF = 10ns; CL = 50pF and 1 TTL Load
LIMITS CDP1826C (NOTE 1) MIN (NOTE 2) TYP
PARAMETER READ - CYCLE TIMES (FIGURES 4 AND 5) Address to TPA Setup Address to TPA Hold Access from Address Change TPA Pulse Width Output Valid from MRD Access from Chip Select CEO Delay from TPA MRD to CEO Delay Output High Z from Invalid MRD Output High Z from Chip Deselect NOTES: Edge tASH tAH TAA tPAW tAM tAC tCA tMC tRHZ tSHZ
MAX
UNITS
100 100 200 75 -
500 500 500 150 -
1000 1000 1000 300 125 225
ns ns ns ns ns ns ns ns ns ns
1. Time required by a limit device to allow tor the indicated function. 2. Typical values are or TA = 25oC and nominal VDD.
A0 - A5
HIGH ORDER ADDRESS BYTE tASH tAH
LOW ORDER ADDRESS BYTE tAA
TPA tPAW MRD tAC tRHZ
CS1 - CS2
VALID CHIP SELECT
tCA CEO tMC BUS HIGH IMPEDANCE tAM VALID DATA
tSHZ
FIGURE 4. TIMING WAVEFORMS FOR READ CYCLE 1
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CDP1826C
A0 - A5
HIGH ORDER ADDRESS BYTE
LOW ORDER ADDRESS BYTE
tAA
MRD
tAC CS1 * CS2
tRHZ
VALID CHIP SELECT
tSHZ
HIGH IMPEDANCE BUS tAM VALID DATA
FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH)
Dynamic Electrical Specifications At TA = -40 to +85oC, VDD = 5V 5%,Input tR, tF = 10ns; CL = 50pF and 1 TTL Load
LIMITS CDP1826C (NOTE 1) MIN (NOTE 2) TYP
PARAMETER WRITE - CYCLE TIMES (FIGURES 6 AND 7) Address to TPA Setup, High Byte Address to TPA Hold Address Setup, Low Byte TPA Pulse Width Chip Select Setup Write Pulse Width Write Recovery Data Setup Data Hold from End of MWR Data Hold from End of Chip Select NOTES: tASH tAH TASL tPAW tCS tWW tWR tDS tDH1 tDH2
MAX
UNITS
100 100 500 200 700 300 100 400 100 125
250 350 200 200 50 50
-
ns ns ns ns ns ns ns ns ns ns
1. Time required by a limit device to allow tor the indicated function. 2. Typical values are for TA = 25oC and nominal VDD.
6-53
CDP1826C
A0 - A5
HIGH ORDER ADDRESS BYTE tASH tAH
LOW ORDER ADDRESS BYTE
tASL
tWR
TPA tPAW tWW MWR
tCS CS1 * CS2 VALID CHIP SELECT
tDS BUS DATA IN STABLE
tDH1, tDH2
FIGURE 6. TIMING WAVEFORMS FOR WRITE-CYCLE 1
A0 - A5
HIGH ORDER ADDRESS BYTE
LOW ORDER ADDRESS BYTE
tASL tWR tWW MWR
tCS CS1 * CS2 VALID CHIP SELECT
tDS BUS DATA IN STABLE
tDH1, tDH2
FIGURE 7. TIMING WAVEFORMS FOR WRITE-CYCLE 2 (TPA = HIGH)
6-54
CDP1826C
Data Retention Specifications
At TA = -40 to +85oC, see Figure 8 LIMITS TEST CONDITIONS VDR (V) VDR 2.5 tDD tCDR tRC 2.5 tR, tF 5 1 A 5 600 ns 5 600 ns 5 25 A VDD (V) (NOTE 1) TYP 2 CDP1826C
PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current Chip Deselect to Data Retention Time Recovery to Normal Operation Time VDD to VDR Rise and Fall Time NOTE: 1. Typical values are or TA = 25oC and nominal VDD.
MIN -
MAX 2.5
UNITS V
DATA RETENTION MODE VDD 0.95 VDD VDR tCDR tF tR tRC 0.95 VDD
CS1 VIH VIL VIL VIH
FIGURE 8. LOW VDD DATA RETENTION TIMING WAVEFORMS
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